Dynamic random access memory (DRAM) is ubiquitous in modern computing systems. DRAM is ubiquitous because of its relatively low cost, high capacity/density and high speed. The density benefit largely derives from the fact that each cell for storing a data bit requires only a capacitor and single transistor. This is significantly less hardware than required per cell for a static random access memory (SRAM), for example. However, the storage of the data bit on the capacitor of the cell implies a power consumption cost. This is because the capacitor charge may leak over time, causing the cell to lose its value. Consequently, the capacitor must be “refreshed” periodically to retain its value. This involves reading the current value from the cell and writing it back to the cell to “refresh” its value. The refresh operation consumes additional power over other memory technologies that do not require refresh. Refresh may contribute to a significant percentage of the energy consumption of a DRAM, e.g., approximately 20%, and may degrade system performance, e.g., approximately 30%, depending upon the demand for DRAM access by the system.
U.S. Pat. No. 5,469,559, issued to one of the present co-inventors, describes a memory controller and method for refreshing a selected portion of a DRAM that does not contain valid data. This may reduce the amount of power consumed by refreshing, which is needless for invalid data.
The present inventors provide embodiments of a DRAM controller that provide further benefits. The additional benefits are enjoyed primarily by recognition by the inventors of the fact that many operating systems “sanitize” deallocated memory by writing zeroes to it in order to increase system security by preventing a hacker and/or the next user to whom the memory is allocated from seeing the data of the first user, for example.